The present invention relates to integrated circuits.
Integrated circuits (ICs), such as field programmable gate arrays (FPGA) or application specific integrated circuits (ASIC), usually comprise an input unit (also referred to as input cell or input block) to receive an input signal from external with respect of the integrated circuit, a processing unit (also referred to as logic core) to receive and process the sampled comparator output signal, and an output unit to receive a data signal from the processing unit, to derive therefrom an output signal, and to provide the output signal to external with respect of the integrated circuit. The input unit generally comprises a level comparator for comparing the level of the input signal and correspondingly providing a comparator output signal, and a sampling unit (e.g. flip-flop) coupled to the level comparator for sampling the comparator output signal. Typically, the IC has multiple input units and/or multiple output units but may also only have one input and/or output unit.